This is similar, but after the rising clock edge.

这很相似，但在时钟上升沿之后。

But let's assume we have some data here and your clock edge comes, then it's switched to the output.

但是让我们假设我们这里有一些数据并且您的时钟边沿来了，然后它切换到输出。

So when the clock edge rises, both of these flip-flops will hand the value at D over to the Q output.

因此，当时钟边沿上升时，这两个触发器都会将 D 的值传递给 Q 输出。

So we can see here that we have the clock edge and here again is a duration specified TPLH, which says, no, TH here.

所以我们可以在这里看到我们有时钟边沿，这里又是一个持续时间指定的 TPLH，这里说的是，不，TH。

You can see here that the clock goes high, but at the time here, the signal on D already needs to be high even before the clock occurs, the clock edge occurs.

你可以在这里看到时钟变高，但此时，D 上的信号甚至在时钟出现之前就已经需要变高了，时钟边沿出现了。

Now, what about the setup and hold times? The setup time describes the duration, how long before a rising edge, a rising clock edge occurs, that a stable signal needs to be present at the input.

现在，建立时间和保持时间如何？设置时间描述持续时间，即上升沿、上升时钟沿出现之前的持续时间，输入端需要出现稳定信号。