同步动态随机访问内存（synchronous dynamic random-access memory，简称SDRAM）是有一个同步接口的动态随机访问内存（DRAM）。通常DRAM是有一个异步接口的，这样它可以随时响应控制输入的变化。而SDRAM有一个同步接口，在响应控制输入前会等待一个时钟信号，这样就能和计算机的系统总线同步。时钟被用来驱动一个有限状态机，对进入的指令进行流水线(Pipeline)操作。这使得SDRAM与没有同步接口的异步DRAM(asynchronous DRAM)相比，可以有一个更复杂的操作模式。

Synchronous dynamic random-access memory (SDRAM) is any dynamic random-access memory (DRAM) where the operation of its external pin interface is coordinated by an externally supplied clock signal. DRAM integrated circuits (ICs), between the mid-1970s and -1990s typically had an asynchronous interface, where responses to changes in control signal inputs occur as soon as they are received. SDRAM has a synchronous interface, meaning that a clock signal must be received before it responds to the control inputs. The interfaces of SDRAM ICs is therefore synchronous to the clock signal used. In the family of devices standardized by JEDEC, which are called synchronous DRAMs (SDRAMs), the clock signal is used to drive an internal finite state machine that pipelines incoming commands. The memory is divided into several independent sections of memory called banks, allowing the device to operate on several memory access commands at a time, provided the commands are independent of each other (in an interleaved fashion). This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs.