在集成电路设计中，逻辑综合（英语：logic synthesis）是所设计数字电路的高抽象级描述，经过布尔函数化简、优化后，转换到的逻辑门级别的电路连线网表的过程。

通常，逻辑综合的信息来源是硬件描述语言——主要是VHDL和Verilog等，设计人员通常使用硬件描述语言来进行电路的高级抽象（通常是数字电路寄存器传输级的数据、行为）描述数字电路的逻辑功能，这样他们可以把更多精力投入功能方面的设计，而避免在一开始就研究可能极其复杂的电路连线。

然而，从电路的高级抽象描述到实际连线网表，并不是一项简单的工作。在以前，这需要设计人员完成逻辑函数的创建、简化、绘制逻辑门网表等诸多步骤。随着电路的集成规模越来越大，人工进行逻辑综合变成了一项十分繁琐的任务。

In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer program called a synthesis tool. Common examples of this process include synthesis of HDLs, including VHDL and Verilog. Some synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.