延迟间隙是计算机体系结构中一个指令间隙，在前一条指令没有执行完毕的情况下，处理器内部指令流水线上该指令间隙的执行不会修改处理器的状态。这种技术常用于DSP与早期的RISC体系结构。最常见的是下文描述的分支延迟间隙。另外还有过存储延迟间隙，即在存储内存的指令之后跟一个延迟间隙，现在已经基本不用了。

当一个分支指令之后的延迟间隙指令，在指令流水线中被称作分支延迟间隙（branch delay slot）。常见于DSP体系结构与老式的RISC体系结构。MIPS、PA-RISC、ETRAX CRIS、SuperH、SPARC等RISC体系结构在分支后有一个延迟间隙。PowerPC、ARM、DEC Alpha没有采用分支延迟间隙。DSP具有单个分支延迟间隙的有VS DSP、µPD77230、TMS320C3x。SHARC DSP与MIPS-X使用两个分支延迟间隙。

In computer architecture, a delay slot is an instruction slot that gets executed without the effects of a preceding instruction. The most common form is a single arbitrary instruction located immediately after a branch instruction on a RISC or DSP architecture; this instruction will execute even if the preceding branch is taken. Thus, by design, the instructions appear to execute in an illogical or incorrect order. It is typical for assemblers to automatically reorder instructions by default, hiding the awkwardness from assembly developers and compilers.