Delay-locked loop
（重定向自Delay lock loop）
![The delay locked loop is a variable delay line whose delay is locked to the duration of the period of a reference clock.
Depending on the signal processing element in the loop (a flat amplifier or an integrator),the DLL loop can be of 0th order type 0 or of 1st order type 1.](/Images/godic/202501/08/Delay_locked_loop,_0th_order_type_0_and_1st_order_type_13458.png")
In electronics, a delay-locked loop (DLL) is a digital circuit similar to a phase-locked loop (PLL), with the main difference being the absence of an internal voltage-controlled oscillator, replaced by a delay line.
A DLL can be used to change the phase of a clock signal (a signal with a periodic waveform), usually to enhance the clock rise-to-data output valid timing characteristics of integrated circuits (such as DRAM devices). DLLs can also be used for clock recovery (CDR). From the outside, a DLL can be seen as a negative-delay gate placed in the clock path of a digital circuit.